A semiconductor memory cell, which is based on the principle of charge trapping, has a memory transistor, which is positioned on a top side of a semiconductor body (substrate) or of a semiconductor layer, which is provided with a gate electrode arranged between the source and drain regions formed in the semiconductor material. The gate electrode is insulated from the semiconductor material by a dielectric material. Particularly in the case of a charge trapping memory cell, between the gate electrode and the source region and between the gate electrode and the drain region there is a layer sequence which comprises a memory layer. The memory layer serves to trap charge carriers, i.e., electrons or holes, between the boundary layers. The material of the memory layer is selected in such a way that it has a lower energy band gap, i.e., the gap between valence band and conduction band, than that of the boundary layer material. Therefore, the charges will remain localized on the storage layer. The material selected for the boundary layers is usually an oxide, in particular silicon dioxide, whereas a nitride, in particular silicon nitride, is selected for the memory layer material. A structure of this type is also known as an “ONO” structure of “SONOS” transistors. Charge trapping memory cells of this type are well known and have been described in a wide range of publications, e.g., the German patent application DE 199 03 598.9, in the name of the same Applicant.
Field effect transistors of the SONOS type described above are preferably used in silicon semiconductor memory technology as nonvolatile memory elements, i.e., EEPROM. Field effect transistors are preferred to other types of transistors, e.g., transistors having a floating gate, because: they have a simpler cell structure, they are relatively inexpensive to fabricate, and they have a lower defect density. As has also emerged, in transistors having a transistor structure of this type, defects generally have less effect on the functioning of the memory element. Furthermore, memory cells with a structure of the SONOS type have the crucial advantage that adjacent memory cells interact with one another to a lesser extent, which is the consequence in particular of a lower capacitive coupling. However, specifically capacitive coupling of this type constitutes a serious problem in the context of ongoing miniaturization, and this problem is the subject of intensive research in the field of memory cells with a floating gate, in particular in the form of multilevel transistors, as what is known as floating gate/floating gate interference.
In view of the advantageous properties of charge trapping memory cells which have been listed above, considerable efforts are being devoted to further improving this memory technology: a focal point with a view to further reducing the size of the memory transistors, is to improve the data retention, i.e., retention time, and increase the trapping probability of charge carriers in the trapping dielectric. Currently, a number of different solution approaches are being pursued.
One solution approach aimed at improving the charge trapping memory cells of the SONOS type consists in replacing the top dielectric, i.e. the dielectric boundary layer of the dielectric memory layer that is remote from the substrate, with a material possessing a higher dielectric constant and replacing the material of the gate electrode with a material possessing a higher electron work function (cf. the above-referenced German patent application; C. H. Lee et al. IEDM 2003; C. H. Lee et al. US patent application US 2003/0123307 A1).
With regard specifically to the data retention of charge trapping memory cells, it is important that the injected charge carriers be trapped in deep impurities, i.e., impurities which in energy terms are at a deep location in the band gap between valence band and conduction band. In this regard where the charge carriers have to be trapped in deep impurities, the Si3N4/SiN layer, which is customarily used for the memory layer, presents a problem, with regard to the desire to constantly reduce the minimum feature size, since it has a relatively small number of deep impurities and a relatively low efficiency in terms of trapping charge carriers and therefore, it possess restricted data retention.
Previous attempts to increase the efficiency of charge trapping, inter alia, focused on modifying the band gap between valence band and conduction band by using a silicon-richer phase in the SiN; wherein the SiN is typically deposited, via a low pressure chemical vapor deposition (LPCVD) technique, in such a way as to increase the number of trapping centers which can be achieved for the injected charge carriers (cf. T.-S. Chen et al., Electr. Dev. Lett., IEEE Vol. 25, No. 4 (2004) page 205). However, this approach leaves open the question as to whether the Si-richer phases actually generate further deep impurities, since these phases can also lead to Si—Si bonds. Furthermore, this Si-richer phase can lead to an increase in the leakage current. In addition, the data retention achieved by this method is unsatisfactory.
In another approach, it is attempted to combat these problems using a SiC:O trapping layer (cf. T. C. Chang et al., Appl. Phys. Lett. Vol. 84, No. 12, (2004) page 2094). However, these attempts have tended to lead to a reduction in the size of the storage window, since the oxygen doping saturates the deep impurities. Moreover, a layer thickness of 20 nm appears much too large when considering that in years to come the minimum feature sizes of the memory elements are to be scaled into the range of 60 nm.
SONOS or SANOS semiconductor memory cells of this type consist of: a tunnel oxide layer with an approximate thickness of 2.5 nm, a second oxide layer with an approximate thickness of 6 nm and, an LPCVD-SiN layer, with an approximate thickness of 6-8 nm, which is deposited between the two oxide layers.